Low Power , All - Digital Fractional - N Frequency Synthesizers for Multi - GHz Applications

Despite their high degree of reconfigurability and friendliness to technology scaling, traditional ADPLL-based frequency synthesizers tend to come at the price of increased power consumption at their feedback path, compared to charge-pump based solutions. The main power consumption bottleneck is the TDC that operates at the high output frequency rate. A modified version of the ADPLL architecture, that applies phase prediction and aligns the input and output clock edges by means of a digital-to-time converter (DTC), allows the operation of the phase detection entirely at the reference clock rate. To demonstrate the potential of the low-power phase prediction ADPLL architecture, two ADPLL test chips were designed, comprising a 2.5-5 GHz ring DCO and a wideband 10-16 GHz LC-DCO respectively. The two chips make use of the same DTC-TDC pair that consists identical delay generic cells for matched DTC and TDC gain values. The ADPLLs target multiple standards of wireline communication interfaces. At its typical configuration, the ring DCO ADPLL is expected to exhibit a power consumption of 3.9-5.3 mW resulting to a FoM of -164 dB, lower than any other reported ring-oscillator-based fractional-N PLL. The LC-DCO ADPLL power consumption varies from 10.2 to 13.8 mW and is the first fractional-N synthesizer among those targeting wireline communication for this range of frequencies. Additionally, this work introduces a cyclic DTC-TDC pair that can be rotated randomly in order to apply dynamic element matching of its elements and alleviate mismatch-induced spurs at low offsets of the spectrum in near-integer operation. The structure also allows dithering of the DTC control code in order to reduce quantization-induced spurs.